The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing high speed first-in-first-out (FIFO) structures.
FIFOs are used in a variety of circuit applications. For example, data communication circuits use FIFO structures to address different system timing requirements. A serializer, for example, employs an internal clock that may not be synchronized with an external clock used to supply data to the circuit. A FIFO is used to transfer the data from the external clock regime to the internal clock regime. Typically, such a FIFO includes a number of registers that operate in response to a write pointer and a read pointer. An external clock usually provides or controls the write pointer while an internal clock controls the read pointer. Even though the phase relationship between these two clock domains is arbitrary, conventional FIFO designs require the frequencies of the two clock signals to be the same. There are applications, however, that require one clock domain to be of different frequency compared to the other (e.g., the write clock frequency be half that of the read clock, or vice versa). Furthermore, FIFOs require additional control circuitry to ensure the correct timing relationship between the write pointers and the read pointers. For example, the FIFO pointers must be set to the correct initial positions upon start-up, and then reset when any one of a number of conditions occur (e.g., overflow, loss of write clock, etc.). Also, FIFO pointers need to be monitored for a number of different purposes including detection of overflow conditions, detection of loss of external (write) clock, abnormalities in pointer operation, etc.
There is a need for improved method and circuitry for implementing high speed FIFO structures that meet all of the above requirements.
The present invention provides methods and circuitry for implementing high speed FIFO structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
Accordingly, in one embodiment, the present invention provides a FIFO that includes a plurality of registers; a write pointer circuit having an input that receives a write clock signal and a plurality of outputs that respectively couple to the plurality of registers, the write pointer circuit generates a write pointer signal at a first frequency; and a read pointer circuit having an input that receives a read clock signal and a plurality of outputs that respectively couple to the plurality of registers, the read pointer circuit generates a read pointer signal at a second frequency that is different than the first frequency. In a specific embodiment, the frequency of the write pointer signal is half of the frequency of the read pointer signal. In another embodiment, the FIFO further includes a programming circuit that is configured to programmably vary the frequency of the write pointer signal.
In another embodiment the present invention provides a method of operating a FIFO pointer circuit that includes coupling a plurality of shift registers in a circular fashion; and applying a rising edge and a falling edge of a pointer clock signal to clock inputs of the plurality of shift registers in an alternating fashion.
In a further embodiment, the present invention provides a FIFO pointer reset circuit that includes a clock present detector coupled to receive a read clock and a write clock and configured to generate a CKPRES signal indicating status of the write clock; and logic circuit coupled to receive a reset signal, the CKPRES signal, the write clock and the read clock, and configured to generate a write pointer reset signal and a read pointer reset signal in response thereto. More specifically, the logic circuit further receives a lock detect signal indicating phase status of the read clock, the lock detect signal being logically combined with other input signals to the logic circuit. The FIFO pointer reset circuit generates the write pointer reset signal and the read pointer reset signal to respectively reset a write pointer circuit and read pointer circuit when the CKPRES signal indicates loss of the write clock, or when the reset signal is asserted, or when the lock detect signal indicates a no-lock condition for the read clock.
In yet another embodiment, the present invention provides a method of resetting FIFO pointer circuits that includes detecting the presence of a write clock signal and generating a CKPRES signal; detecting the lock status of a read clock signal phase-locked loop and generating a LCKDET signal; receiving a reset signal; and logically combining the CKPRES, the LCKDET and the reset signal to reset the FIFO pointer circuits when the write clock signal is lost, or when the read clock is not locked, or when the reset signal is asserted.
In another embodiment, the present invention provides a write clock present detector for a FIFO circuit, the write clock present detector includes a read shift register having a first plurality of serially-coupled registers and configured to shift a read flag signal in response to a read clock; a write shift register having a second plurality of serially-coupled register and configured to shift a write flag signal in response to a write clock; and a logic circuit coupled to an output of the read shift register and an output of the write shift register, and configured to logically combine the write flag signal with the read flag signal to generate a write clock present detect output signal. In a specific embodiment, the first plurality of registers in the read shift register is larger in number compared to the second plurality of register in the write shift register.
In a further embodiment, the present invention provides a method of detecting the presence of a write clock for a FIFO circuit, the method including propagating a read flag signal through a read shift register in response to a read clock; propagating a write flag signal through a write shift register in response to the write clock; and comparing an output of the read shift register with an output of the write shift register to generate a write clock present output signal.
In another embodiment, the present invention provides a FIFO pointer circuit including a serial chain of N registers coupled in circle and configured to shift a pointer signal in response to a pointer clock; and a pointer malfunction detector having a logic circuit with N inputs respectively coupled to N outputs of the N registers, wherein, the logic circuit is configured to detect lack of the pointer signal or presence of multiple pointer signals.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the FIFO circuitry according to the present invention.